Aldec Adds Support for Cadence TestBuilder C++ Testbench Libraries

Henderson Nevada, October 7th, 2002 - Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices, today announced support for Cadence’s open source TestBuilder to provide its users with reusable, transaction-based verification. Riviera’s mixed language simulator has been enhanced to support high-level testbench tools. By extending its support to include TestBuilder, Riviera users can now create testbenches in C++ code and concentrate on desired design behavior instead of implementation details. Riviera’s support for TestBuilder lets designers develop testbenches at a system-level perspective, saving design time. The ability to re-use C++ testbenches also accelerates the development cycle of future designs.

Advantages of Use
For the most complex ASIC designs, it is no longer practical to develop testbenches in either VHDL or Verilog because the stimulus for each signal must be accounted for during simulation. By developing the testbenches in C++, its object-oriented capability lets designers develop stimuli information at a much higher level of abstraction. Instead of driving individual signals and schedule events, the TestBuilder libraries contain useful functions that automate many tedious operations, such as constrained randomization, by operating in a transaction-based mode.

“Most ASIC designs need a more modular method of developing testbenches. Writing testbenches in C++ not only increases the testbench performance, but also enables the designer to write more detailed testbenches in a shorter period of time,” stated Eric Seabrook, Product Marketing Manager for Aldec.

Accelerated Verification Through Riviera IPT
TestBuilder’s use of pure C++ code with standard C++ compilers allows the user to compile the testbench to a platform-specific native code and execute simulation at the maximum speed in a cycle-based mode. The speed improvement can be even further accelerated by using Riviera IPT, allowing for a hardware/software co-verification environment. The RTL code can be compiled into the hardware board, leaving the C++ testbench in software. The use of the more-efficient C++ testbenches, together with the hardware acceleration of Riviera IPT, typically results in an overall performance acceleration of 100 to 1000x faster.

Simulation Interface
The C++ interface provides access to the TestBuilder libraries used for modeling memories, queues, FIFOs and other commonly used design structures. They communicate with the simulated HDL models in Riviera via an optimized CHPI interface that is masked, making it ideal for driving mixed language designs where a language-specific interface would normally be required. The C++ class library handles this communication so there is no need develop a Verilog (PLI) or VHDL (VHPI) interface code.

Availability
Riviera is available today based on a floating O/S independent license that supports UNIX, Windows and Linux. It includes an industry-proven mixed VHDL and Verilog simulation engine, which supports IEEE VHDL 1076-87/93 and Vital 2000 in addition to Verilog 1376-95 and 2001. Code Coverage, Design Profiler and interfaces to all leading EDA tools are included in Riviera’s product configuration. Riviera is sold directly by Aldec in the U.S. and authorized international distributors. A FREE evaluation copy of Riviera, go to www.aldec.com/riviera.

TestBuilder is shareware software from Cadence Design Systems, Inc. available under the open source code licensing agreement. TestBuilder 1.0 libraries in source form are available now and can be downloaded from www.testbuilder.net. The pre-compiled libraries, ready for use with Riviera, can also be downloaded from Aldec’s website and includes detailed documentation for use.

About Aldec
Aldec, Inc., an 18-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers’ designs. Additional information about Aldec is available at http://www.aldec.com.

Riviera is a trademark of Aldec, Inc. Cadence is a registered trademark of Cadence Design Systems, Inc. All other trademarks or registered trademarks are property of their respective owners.

Contact:        
Eric Seabrook
Aldec, Inc.
(702) 990-4400 ext. 224        
erics@aldec.com